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Keynotes
Talk Title is Coming Soon
Presenter: Shigeru Shiratake, Senior Vice President, DRAM Technology & Products at Micron
Bio: Shigeru Shiratake is the Senior Vice President of the DRAM Technology and Product Development organization. Shiratake joined Micron in 2013 as the Section Director of the DRAM process integration organization. Prior to joining Micron, Shiratake was an executive of Elpida Memory (acquired by Micron in 2013) between 2005 – 2013, leading several DRAM programs. Shiratake experience spans 38 years in the memory technology sector and includes additional leadership positions with Renesas Technology Inc. and Mitsubishi Electric Corp. Shiratake is a published author of many technical papers, holding dozens of patents pertaining to semiconductor technology. Shiratake holds a Master of Science in Electronic Engineering from Yamaguchi University, Japan.
AI Influence on Future High Performance Computer Architectures
Presenter: David Nellans, Senior Director, Architecture Research, NVIDIA
Tutorial
Machine Learning-Based Interface Design for Equalization-Less (or Minimal-Equalization) Channel Compensation
Presenters: Tejasvi Anand, Associate Professor, Oregon State University
Ramin Javadi, Ph.D. Candidate, Oregon State University
Jong Hyun (John) Kim, Ph.D. Student, Oregon State University
Abstract:
High-speed wireline communication links are critical for meeting the performance demands of large language models (LLMs) in modern data centers. However, channel non-idealities significantly degrade link efficiency and limit achievable data rates. In this talk, we present a machine learning–based approach that employs a classifier to learn channel non-idealities and accurately predict transmitted information with a very low bit error rate. We discuss the types of features extracted from the received data and the methodology used to train the classifier using these features.
Measured silicon results demonstrate that the proposed machine learning approach with minimal equalization can compensate for up to 47 dB of channel loss while operating a 25 Gb/s transceiver, including the on-chip classifier, implemented in 16 nm FinFET technology. We further show how the same framework can learn and compensate for crosstalk in a 4-lane wireline link operating at an aggregate data rate of 100 Gb/s. Finally, we present a live demonstration illustrating how MATLAB and Python libraries can be used to train the classifier and automatically convert the trained model into synthesizable Verilog code.
Bio:
Tejasvi Anand (Top) is an Associate Professor in the department of Electrical Engineering and Computer Science at the Oregon State University, Corvallis, OR, USA. He received his Ph.D. degree in Electrical Engineering from the University of Illinois at Urbana-Champaign, IL, USA in 2015, and M.Tech. degree (distinction) in Electronics Design and Technology from the Indian Institute of Science, Bangalore, India, in 2008. From 2008 to 2010, he worked as an Analog Design Engineer at Cosmic Circuits (now Cadence), Bengaluru. His research focuses on wireline communication, and frequency synthesizers with an emphasis on energy efficiency.
Ramin Javadi (Middle) is a Ph.D. candidate in electronics at Oregon State University, Corvallis, OR, USA. In Fall 2025, he was a hardware technology intern at Apple Inc., Cupertino, CA, USA. He also serves as a reviewer for the IEEE Transactions on Circuits and Systems I (TCAS-I). His research focuses on energy-efficient, high-speed wireline communication systems.
Jong Hyun (John) Kim (Bottom) is currently pursuing a Ph.D. degree in Electrical Engineering at Oregon State University, Corvallis, OR. His research interests include next-generation wireline system architectures and area-efficient, low-power machine-learning-inspired signal equalizers. He also serves as a reviewer for the IEEE Journal of Solid-State Circuits, Transactions on Circuits and Systems I (TCAS-I), and Transactions on Circuits and Systems II (TCAS-II).
Invited Talks
AI-Driven Design and Synthesis of High-Performance Analog Integrated Circuits
Presenter: Mohamed Elamien, Assistant Professor, McMaster Unviersity
Manager, Micro- and Nano-Systems Laboratory
Associate Editor, International Journal of Circuit Theory & Applications, Wiley
Abstract: Artificial intelligence (AI) is opening new pathways for the automated design and synthesis of high-performance analog integrated circuits. Yet analog design remains notoriously difficult to automate owing to strong device-level interactions, conflicting performance trade-offs, and multi-objective constraints. This talk reviews traditional circuit sizing methods alongside emerging AI-based approaches that enable more efficient exploration of high-dimensional design spaces. A case study illustrates how figure-of-merit definitions can strongly influence optimization outcomes and practical design decisions. The discussion concludes by showing how symbolic analysis and agentic AI frameworks can embed circuit knowledge into practical workflows, pointing toward more scalable and intelligent analog IC design automation.
Bio: Dr. Mohamed B. Elamien is an Assistant Professor in the Department of Electrical and Computer Engineering at McMaster University, Canada. His research interests include analog and mixed-signal integrated circuit design, circuit theory, AI-driven analog design automation, and high-performance low-power circuits for biomedical, and sensing applications. He received his Ph.D. in Electrical and Computer Engineering from the University of Calgary in 2021, followed by postdoctoral work on high-speed digitizers for astronomical instrumentation. He also worked at Synopsys Inc. as a Senior Analog and Mixed-Signal Circuit Design Engineer, where he contributed to advanced SerDes IP development. He serves as an Associate Editor for the International Journal of Circuit Theory and Applications.
Scaling 2D CMOS: From Transistors to 3D Integrated Systems
Presenter: Saptarshi Das, Ackley Professor of Engineering and MRI Fellow, The Pennsylvania State University
Abstract: Two-dimensional (2D) semiconductors provide a powerful platform for pushing transistor scaling beyond the limits of conventional CMOS while opening new pathways for integration. In this talk, I will highlight recent advances in scaling 2D field-effect transistors, with particular emphasis on achieving high-performance p-type devices to enable true CMOS operation and their implementation in functional logic circuits. I will then highlight the progress in monolithic and heterogeneous 3D integration, including three-tier 2D FETs, 3D CMOS, 3D heterogeneous platforms for near-sensor computing, self-powered 3D systems with integrated silicon photovoltaics, and 3D SRAM architectures. Finally, I will briefly discuss additional functional uses of 2D materials, including on-chip thermometry and their role as robust hard masks for advanced patterning. Together, these advances illustrate the transition of 2D materials from scaled transistors to fully integrated 3D electronic systems.
Bio: Dr. Das received his B.Eng. degree (2007) in Electronics and Telecommunication Engineering from Jadavpur University, India, and Ph.D. degree (2013) in Electrical and Computer Engineering from Purdue University. He was a Postdoctoral Research Scholar (2013-2015) and Assistant Research Scientist (2015-2016) at Argonne National Laboratory (ANL). Dr. Das joined the Department of Engineering Science and Mechanics (ESM) at Penn State University in January 2016. Dr. Das was the recipient of the Young Investigator Award from the United States Air Force Office of Scientific Research in 2017 and the National Science Foundation (NSF) CAREER award in 2021. Das Research Group at Penn State leads a new multidisciplinary area of science, namely biomimetic sensing, neuromorphic computing, and hardware security inspired by natural designs found in the animal world that allow evolutionary success in resource-constrained environments.
Talk Title is Coming Soon (related to hardware security)
Presenter: Tamara Schmitz, Director of Product Security, Micron Technology
Talk Title is Coming Soon (related to advanced photolithography)
Presenter: Michael Lercel, Senior Director, Strategic Marketing, ASML